Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi. Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. In 2017 IEEE International Conference on IC Design and Technology, ICICDT 2017, Austin, TX, USA, May 23-25, 2017. pages 1-4, IEEE, 2017. [doi]
Abstract is missing.