Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis. IEEE Access, 7:75500-75514, 2019. [doi]

Abstract

Abstract is missing.