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Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL

Nectarios Koziris, Theodore Andronikos, George Economakos, George K. Papakonstantinou, Panayotis Tsanakas. Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. In Louis O. Hertzberger, Peter M. A. Sloot, editors, High-Performance Computing and Networking, International Conference and Exhibition, HPCN Europe 1997, Vienna, Austria, April 28-30, 1997, Proceedings. Volume 1225 of Lecture Notes in Computer Science, pages 888-897, Springer, 1997.

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