Andrzej Krasniewski. Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs. In Luca Fanucci, editor, 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008. pages 250-255, IEEE, 2008. [doi]
Abstract is missing.