Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis - researchr publication

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Vyas Krishnan, Srinivas Katkoori. Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis. In 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India. pages 641-646, IEEE Computer Society, 2008. [doi]

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