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PositGen-A Verification Suite for Posit Arithmetic

Annarao Kulkarni, Shashikala Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine. PositGen-A Verification Suite for Posit Arithmetic. In 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021. pages 204-209, IEEE, 2021. [doi]

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