A VLSI-efficient signed magnitude comparator for { 2n-1, 2n, 2n +2n+1-1} RNS - researchr publication

researchr

You are not signed in
Sign in
Sign up

Sachin Kumar, Chip-Hong Chang. A VLSI-efficient signed magnitude comparator for { 2n-1, 2n, 2n +2n+1-1} RNS. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 1966-1969, IEEE, 2016. [doi]

Abstract is missing.

runs on WebDSL