DD-Tuning Scheme With Speed-Margining for Low-Power SRAM

Ya-Chun Lai, Shi-Yu Huang, Hsuan-Jung Hsu. DD-Tuning Scheme With Speed-Margining for Low-Power SRAM. J. Solid-State Circuits, 44(10):2817-2823, 2009. [doi]

Abstract

Abstract is missing.