Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks - researchr publication authors

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Christophe Layer, Kotb Jabeur, Stephane Gros, Laurent Becker, Pierre Paoli, Fabrice Bernard-Granger, Virgile Javerliac, Bernard Dieny. Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks. In IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015. pages 1-4, IEEE, 2015. [doi]

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