Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA

Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer. Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 405-408, IEEE, 2007. [doi]

@inproceedings{LayerSP07,
  title = {Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA},
  author = {Christophe Layer and Daniel Schaupp and Hans-Jörg Pfleiderer},
  year = {2007},
  doi = {10.1109/ISCAS.2007.378475},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2007.378475},
  tags = {optimization, data-flow, context-aware},
  researchr = {https://researchr.org/publication/LayerSP07},
  cites = {0},
  citedby = {0},
  pages = {405-408},
  booktitle = {International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA},
  publisher = {IEEE},
}