A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface - researchr publication authors

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Chang-Kyo Lee, Min-Su Ahn, Daesik Moon, Kiho Kim, Yoon-Joo Eom, Won Young Lee, Jongmin Kim, Sanghyuk Yoon, Baekkyu Choi, Seokhong Kwon, Joon Young Park, Seung-Jun Bae, Yong-Cheol Bae, Jung Hwan Choi, Seong-Jin Jang, Gyo-Young Jin. A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. In Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015. pages 182, IEEE, 2015. [doi]

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