A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation

Won Young Lee, Lee-Sup Kim. A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation. IEEE Trans. on Circuits and Systems, 59-I(11):2518-2528, 2012. [doi]

Abstract

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