Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

Dong Uk Lee, Shin-Deok Kang, Nak-Kyu Park, Hyun-Woo Lee, Young-Kyoung Choi, Jung Woo Lee, Seung-Wook Kwack, Hyeong Ouk Lee, Won-Joo Yun, Sang-Hoon Shin, Kwan-Weon Kim, Young-Jung Choi, Ye Seok Yang. Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. In 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008. pages 280-281, IEEE, 2008. [doi]

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