Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Switching

Zhentao Li, Shuming Chen. Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Switching. In 10th International Conference on Computer-Aided Design and Computer Graphics, CAD/Graphics 2007, Beijing, China, 15-18 October, 2007. pages 315-320, IEEE, 2007. [doi]

Abstract

Abstract is missing.