A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator

Weitao Li, Fule Li, Jia Liu, HongYu Li, Zhihua Wang. A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 225-228, IEEE, 2017. [doi]

Abstract

Abstract is missing.