Weiping Liao, Lei He. Microarchitecture Level Interconnect Modeling Considering Layout Optimization. J. Low Power Electronics, 1(3):297-308, 2005. [doi]
@article{LiaoH05:0,
title = {Microarchitecture Level Interconnect Modeling Considering Layout Optimization},
author = {Weiping Liao and Lei He},
year = {2005},
doi = {10.1166/jolpe.2005.036},
url = {http://dx.doi.org/10.1166/jolpe.2005.036},
tags = {optimization, layout, modeling},
researchr = {https://researchr.org/publication/LiaoH05%3A0},
cites = {0},
citedby = {0},
journal = {J. Low Power Electronics},
volume = {1},
number = {3},
pages = {297-308},
}