2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process - researchr publication

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Chun-Yu Lin, Ming-Dou Ker. 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 3417-3420, IEEE, 2010. [doi]

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