Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi. Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integration, 43(2):176-187, 2010. [doi]

Abstract

Abstract is missing.