Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits

Loganathan Lingappan, Niraj K. Jha. Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA. pages 418-423, IEEE Computer Society, 2005. [doi]

Abstract

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