Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda. Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. In Farn Wang, editor, Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings. Volume 3299 of Lecture Notes in Computer Science, pages 426-440, Springer, 2004. [doi]
Abstract is missing.