Input-aware statistical timing analysis for VLSI delay test and average design - researchr publication

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Bao Liu. Input-aware statistical timing analysis for VLSI delay test and average design. In IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014, College Station, TX, USA, August 3-6, 2014. pages 1005-1008, IEEE, 2014. [doi]

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