Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan - researchr publication

researchr

You are not signed in
Sign in
Sign up

ZhiPeng Liu, Jinian Bian, Qiang Zhou, Hui Dai. Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. In 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil. pages 279-284, IEEE Computer Society, 2007. [doi]

Abstract is missing.

runs on WebDSL