Wulong Liu, Haixiao Du, Yu Wang 0002, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang. TSV-aware topology generation for 3D Clock Tree Synthesis. In International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013. pages 300-307, IEEE, 2013. [doi]
Abstract is missing.