Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota. Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA. pages 349-354, IEEE Computer Society, 2005. [doi]

The following publications are possibly variants of this publication:

Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clockingChunsheng Liu, Vikram Iyengar. date 2006: 652-657 [doi]

Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency ClockingChunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan. vts 2006: 46-51 [doi]

Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable ClockingChunsheng Liu. ats 2006: 431-436 [doi]

runs on WebDSL