Hardware Design and Verification Techniques for Supply Chain Risk Mitigation

Bao Liu, Yier Jin, Gang Qu. Hardware Design and Verification Techniques for Supply Chain Risk Mitigation. In 14th International Conference on Computer-Aided Design and Computer Graphics, CAD/Graphics 2015, Xi'an, China, August 26-28, 2015. pages 238-239, IEEE, 2015. [doi]

Abstract

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