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Qing Liu, Wei Shu, Joseph S. Chang. A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS. IEEE Trans. VLSI Syst., 25(12):3444-3454, 2017. [doi]
Abstract is missing.