A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic - researchr publication

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Kerry S. Lowe, P. Glenn Gulak. A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. IEEE Trans. on CAD of Integrated Circuits and Systems, 17(5):419-434, 1998. [doi]

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