Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

Daniele Ludovici, Francisco Gilabert Villamón, Simone Medardoni, Crispín Gómez Requena, María Engracia Gómez, Pedro López, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi. Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009. pages 562-565, IEEE, 2009. [doi]

@inproceedings{LudoviciVMRGLGB09,
  title = {Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints},
  author = {Daniele Ludovici and Francisco Gilabert Villamón and Simone Medardoni and Crispín Gómez Requena and María Engracia Gómez and Pedro López and Georgi Nedeltchev Gaydadjiev and Davide Bertozzi},
  year = {2009},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=5090609&arnumber=5090727&count=326&index=113},
  tags = {constraints, design},
  researchr = {https://researchr.org/publication/LudoviciVMRGLGB09},
  cites = {0},
  citedby = {0},
  pages = {562-565},
  booktitle = {Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009},
  publisher = {IEEE},
}