Jeng-Jong J. Lue, Dhananjay S. Phatak. Area x Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation. In 14th IEEE Symposium on Computer Arithmetic (Arith-14 99), 14-16 April 1999, Adelaide, Australia. pages 216-224, IEEE Computer Society, 1999. [doi]
Abstract is missing.