Area-Efficient Area Pad Design for High Pin-Count Chips

Louis Luh, John Choma Jr., Jeffrey T. Draper. Area-Efficient Area Pad Design for High Pin-Count Chips. In 9th Great Lakes Symposium on VLSI (GLS-VLSI 99), 4-6 March 1999, Ann Arbor, MI, USA. pages 78-81, IEEE Computer Society, 1999. [doi]

Abstract

Abstract is missing.