Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. In Nadine Azémard, Lars J. Svensson, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Volume 4644 of Lecture Notes in Computer Science, pages 160-170, Springer, 2007. [doi]
Abstract is missing.