Bjørnar Luteberget, Koen Claessen, Christian Johansen. Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation. In Nikolaj Bjørner, Arie Gurfinkel, editors, 2018 Formal Methods in Computer Aided Design, FMCAD 2018, Austin, TX, USA, October 30 - November 2, 2018. pages 1-9, IEEE, 2018. [doi]
Abstract is missing.