Naresh Maheshwari, Sachin S. Sapatnekar. Efficient Minarea Retiming of Large Level-Clocked Circuits. In 1998 Design, Automation and Test in Europe (DATE 98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France. pages 840, IEEE Computer Society, 1998. [doi]
Abstract is missing.