A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

Ahmed Mahmoud, Pietro Andreani, Ping Lu 0002. A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise. In Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP & International Symposium on System-on-Chip (SoC), Oslo, Norway, October 26-28, 2015. pages 1-4, IEEE, 2015. [doi]

@inproceedings{MahmoudA015,
  title = {A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise},
  author = {Ahmed Mahmoud and Pietro Andreani and Ping Lu 0002},
  year = {2015},
  doi = {10.1109/NORCHIP.2015.7364356},
  url = {https://doi.org/10.1109/NORCHIP.2015.7364356},
  researchr = {https://researchr.org/publication/MahmoudA015},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP & International Symposium on System-on-Chip (SoC), Oslo, Norway, October 26-28, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-6576-5},
}