A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture

Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara. A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. In ICCD. pages 202-205, 1993.

Authors

Hiroshi Makino

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Yasunobu Nakase

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Hirofumi Shinohara

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