Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow - researchr publication bibliographies

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Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown. Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. In Mike Hutton, Joni Dambre, editors, The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings. pages 3-8, ACM, 2006. [doi]

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