Fully Automatic Verifcation and Error Detection for Parameterized Iterative Sequential Circuits

Tiziana Margaria. Fully Automatic Verifcation and Error Detection for Parameterized Iterative Sequential Circuits. In Tiziana Margaria, Bernhard Steffen, editors, Tools and Algorithms for Construction and Analysis of Systems, Second International Workshop, TACAS 96, Passau, Germany, March 27-29, 1996, Proceedings. Volume 1055 of Lecture Notes in Computer Science, pages 258-277, Springer, 1996.

Abstract

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