The following publications are possibly variants of this publication:
- Test-architecture optimization for TSV-based 3D stacked ICsBrandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree. ets 2010: 24-29 [doi]
- Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test accessErik Jan Marinissen. apccas 2010: 544-547 [doi]
- Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICsBrandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree. tcad, 30(11):1705-1718, 2011. [doi]
- Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICsSergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen. itc 2013: 1-10 [doi]