Luis Gustavo Perpetuo Costa Marques, Max Hering de Queiroz, Jean-Marie Farines. Improving a design methodology of synthesizable VHDL with formal verification. In IEEE 7th Latin American Symposium on Circuits & Systems, LASCAS 2016, Florianopolis, Brazil, February 28 - March 2, 2016. pages 51-54, IEEE, 2016. [doi]
Abstract is missing.