Logic circuit design with gates, LUTs and MUXs oriented to mask faults - researchr publication authors

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Anzhela Matrosova, Sergey Ostanin, D. Tretyakov, Natalia Butorina. Logic circuit design with gates, LUTs and MUXs oriented to mask faults. In 2017 IEEE East-West Design & Test Symposium, EWDTS 2017, Novi Sad, Serbia, September 29 - October 2, 2017. pages 1-4, IEEE Computer Society, 2017. [doi]

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