Ken Matsubara, Tsutomu Nagasawa, Yoshinobu Kaneda, Hidenori Mitani, Hiroshi Sato, Takashi Iwase, Yasunobu Aoki, Keiichi Maekawa, Hideaki Yamakoshi, Takashi Ito, Hiroyuki Kondo, Takashi Kono. A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 202, IEEE, 2019. [doi]
@inproceedings{MatsubaraNKMSIA19,
title = {A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications},
author = {Ken Matsubara and Tsutomu Nagasawa and Yoshinobu Kaneda and Hidenori Mitani and Hiroshi Sato and Takashi Iwase and Yasunobu Aoki and Keiichi Maekawa and Hideaki Yamakoshi and Takashi Ito and Hiroyuki Kondo and Takashi Kono},
year = {2019},
doi = {10.23919/VLSIC.2019.8778078},
url = {https://doi.org/10.23919/VLSIC.2019.8778078},
researchr = {https://researchr.org/publication/MatsubaraNKMSIA19},
cites = {0},
citedby = {0},
pages = {202},
booktitle = {2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019},
publisher = {IEEE},
isbn = {978-4-86348-720-8},
}