A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto. A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. IEICE Transactions, 98-C(4):333-339, 2015. [doi]

Authors

Go Matsukawa

This author has not been identified. Look up 'Go Matsukawa' in Google

Yohei Nakata

This author has not been identified. Look up 'Yohei Nakata' in Google

Yasuo Sugure

This author has not been identified. Look up 'Yasuo Sugure' in Google

Shigeru Oho

This author has not been identified. Look up 'Shigeru Oho' in Google

Yuta Kimi

This author has not been identified. Look up 'Yuta Kimi' in Google

Masafumi Shimozawa

This author has not been identified. Look up 'Masafumi Shimozawa' in Google

Shuhei Yoshida

This author has not been identified. Look up 'Shuhei Yoshida' in Google

Hiroshi Kawaguchi

This author has not been identified. Look up 'Hiroshi Kawaguchi' in Google

Masahiko Yoshimoto

This author has not been identified. Look up 'Masahiko Yoshimoto' in Google