Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. In NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010. pages 61-68, IEEE Computer Society, 2010. [doi]

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