The following publications are possibly variants of this publication:
- Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPsHiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. tcad, 30(4):520-533, 2011. [doi]
- Run-time power gating of on-chip routers using look-ahead routingHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang. aspdac 2008: 55-60 [doi]
- Geyser-2: The second prototype CPU with fine-grained run-time power gatingLei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo. aspdac 2011: 87-88 [doi]
- Run-Time Power-Gating Techniques for Low-Power On-Chip NetworksHiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano. In Cristina Silvano, Marcello Lajolo, Gianluca Palermo, editors, Low Power Networks-on-Chip. pages 21-43, Springer, 2011. [doi]
- A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep SignalsKimiyoshi Usami, Naoaki Ohkubo. iccd 2006: 155-161 [doi]
- Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gatingDaisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo. aspdac 2010: 369-370 [doi]