Philippe Maurine, Nadine Azémard, Daniel Auvergne. Gate Sizing for Low Power Design. In Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes, editors, SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC 01), December 3-5, 2001, Montpellier, France. Volume 218 of IFIP Conference Proceedings, pages 301-312, Kluwer, 2001.
Abstract is missing.