SPICE modeling in Verilog-A: Successes and challenges: Invited paper - researchr publication

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Colin C. McAndrew. SPICE modeling in Verilog-A: Successes and challenges: Invited paper. In 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017. pages 22-25, IEEE, 2017. [doi]

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