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P/G pad placement optimization in USB test chips

Vazgen Sh. Melikyan, Karo H. Safaryan, F. A. Aslikyan. P/G pad placement optimization in USB test chips. In 2017 IEEE East-West Design & Test Symposium, EWDTS 2017, Novi Sad, Serbia, September 29 - October 2, 2017. pages 1-3, IEEE Computer Society, 2017. [doi]

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