A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS - researchr publication

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Xiangyu Meng, Weihao Kong, Haifeng Yang, Yecong Li, Xuan Li. A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS. In IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021. pages 1-4, IEEE, 2021. [doi]

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