A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing

Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, L. Benaissa, E. Deschaseaux, M. Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq. A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing. In 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018. pages 245-246, IEEE, 2018. [doi]

Authors

Laurent Millet

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Stéphane Chevobbe

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Caaliph Andriamisaina

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Edith Beigné

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Fabrice Guellec

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Thomas Dombek

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L. Benaissa

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E. Deschaseaux

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M. Duranton

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K. Benchehida

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Mehdi Darouich

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Maria Lepecq

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