D. Montanari, D. DeShazo, G. Yeric. TM: methodology and architecture of a nonvolatile-memory technology development testchip. In Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001. pages 933-936, IEEE, 2001. [doi]
Abstract is missing.