Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system

Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system. SIGARCH Computer Architecture News, 38(4):8-13, 2010. [doi]

Abstract

Abstract is missing.